It has long been desired to execute instructions programmed for a first type of computing machine on another computing machine with dissimilar characteristics without the need for reprogramming. This is similar to translating Chinese poetry into, say, a European language. Rarely, would there be a one-to-one match of words so that some type of approximation or determination of the contexts in which the words occur could be made. To enable the "program" translation from one machine to another, the technique called "emulation" evolved. That is, a facility resident in a target machine was used to "interpret" instructions from another or source machine. Absent a significant one-to-one match between source machine and target machine instructions, the target machine facility attempted to identify the most appropriate target machine instruction or sequence of instructions from the "context" of the source instruction in the source instruction stream.
A program in execution on a machine is termed a "process". During its existence, a process goes through a series of discrete states. Various events can cause a process to change states. However, the manifestation of the process in an operating system is a "process control block" (PCB). The PCB is a data structure containing certain important information about the process. Consequently, the process control block is a source of information that can be utilized by a target machine in order to "interpret" instructions. Such an approach is illustrated by Parks et al, U.S. Pat. No. 4,315,321, "Method and Apparatus for Enhancing the Capabilities of a Computing System". That is, Parks uses information within the control block to interpret which one of several microcode sequences to use in interpreting a given source instruction.
Source and target instructions may also differ simply in the number of bit positions they regularly occupy. Because large computers can execute several functions simultaneously, a large machine instruction consists of several fields. The problem addressed by Nutter, U.S. Pat. No. 3,543,245, "Computer Systems", was that of mapping a source machine instruction into a target machine instruction of different widths in which the contents of the fields were often the same. Nutter observed that the OP code portion of a CPU multifield instruction can be used to select the instruction fields and their microcode instruction order and by appropriate masking, switching, and shifting could accommodate the fact that the target instruction had a width different than that of a source machine instruction. This was described by Nutter in his specification, column 6, line 23, through column 10, line 53, with reference to field selection, while the mapping of randomly ordered fields in the source word into predetermined positions in a target word is set out at column 62, lines 5-36.
Other pertinent references include Cassonnet et al, U.S. Pat. No. 3,997,895, "Data Processing System with a Microprogrammed Dispatcher for Working Either in Native or Non-native Mode", issued 14 Dec. 1976, and Malcolm et al, U.S. Pat. No. 3,698,007, "Central Processor Unit Having Simulative Interpretation Capability", issued 10 Oct. 1972. Cassonnet depicts a microprogrammable switch (130) responsive to preselected bit position contents in an external instruction for having control stored microcode sequences interpreted respectively by the arithmetic logic unit (ALU 1317) or emulator unit (EMU 1316). Malcolm uses the OP code of the simulated instruction as an index into a set of simulator routines, and provides for storage of a base address to which the OP code index is an offset. Lastly, each instruction references only one operand. This configuration directly executes the intent of the non-native instructions.
A class of VLSI implementable computers with reduced instruction sets being driven by a respective data stream and instruction stream from corresponding caches has been described by Radin in "The 801 Minicomputer", appearing in the ACM Proceedings of the Symposium on Architectural Support for Programming Languages and Operating Systems", March 1-3, 1982, in Palo Alto, Calif., at pages 39-47. A similar CPU architecture was described by Patterson and Sequin in "RISC 1: A Reduced Instruction Set VLSI Computer", in the IEEE 8th Annual Symposium on Architecture Conference Proceedings of May 12-14, 1981, at pages 443-449, and in expanded form in IEEE Computer, September 1982 at pages 8-20. In this type of machine, instructions are obtained from an "Instruction Cache", and data is obtained from a separate (data cache), both of which are managed by an LRU information algorithm. Thus, all frequently used functions and data are likely to be found in their respective cache.